1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a redundancy circuit for a defective memory cell.
2. Description of the Related Art
In an ordinary semiconductor memory device, a redundancy circuit is provided for saving the memory device even in a case where a defective cell is contained in at least one of main memory cells or regularly arranged memory cells. The redundancy circuit includes spare memory cells, spare row lines connected to the spare memory cells, a spare row decoder for selectively driving the spare row line to select the spare memory cells, and a control circuit for inhibiting the access operation with respect to the main memory cells and instead activating the spare row decoder when an address signal is generated to specify the row line to which the defective memory cell is connected.
In the semiconductor memory device having the redundancy circuit described above, if the row line to which the defective memory cell is connected is specified by an address signal, the spare memory cell is selected by an output of the spare decoder so as to use the spare memory cell instead of the defective memory cell. In this case, in order to inhibit the use of the row line to which the defective memory cell is connected, all the main row lines are set to logic "L" level when at least one of the spare row lines is selected.
In an erasable and programmable nonvolatile semiconductor memory device (EPROM), after data has been programmed into a selected memory cell, all the row lines are set to logic "L" level too. This operation is effected in order to perform a so-called verify mode operation for checking whether data has been correctly programmed or not by reading out data each time the data is programmed into the memory cell at each address. The verify mode is a kind of read mode. When the EPROM is in a read mode, a read voltage, for example, 5V, is applied to the selected row line, while when in a program mode, a program voltage, for example, 12.5V, is applied to the selected row line. In the verify mode, the programming address is used as a readout address, so that the high voltage of, 12.5V, applied to the row line in the programming mode is kept immediately after data has been programmed. If the verify mode is set immediately after the data programming, data cannot be correctly read out. Therefore the high voltage of selected row line is discharged after data has been programmed.
In the conventional EPROM having the redundancy circuit, the row lines will be discharged when the spare memory cell is used. And the main and spare row lines will be discharged by the reset signal after data has been programmed. A signal for selecting the spare row line and a reset signal for permitting the discharge operation are supplied to a logic gate, and the main row decoder is set into a nonoperable condition and the spare row line is selected in response to an output signal of the logic gate.
In the programming mode, if the address for the defective memory cell is specified the spare row line is selected so as to replace the defective memory cell by the spare memory cell. In this case, a circuit for selecting the spare row line and a circuit for setting the main row decoder into the nonoperable condition are operated in response to an output signal of the logic gate. When the reset signal for setting the verify mode is input, the output signal of the logic gate is set the same state as the spare row line is not selected. Therefore, when the reset operation is finished, the main row decoder is temporarily operated to activate the main row line connected to the defective memory cell, while the logic gate is in response to the spare row line selecting signal. As in the case of the verify mode operation, if data is read out immediately after the data is programmed into the memory cell, data programmed in the spare memory cell and that in the defective main memory cell will be read out at the same time, thus providing erroneous data at the beginning of the readout operation.